The present invention relates generally to the field of computer processor microarchitecture and more particularly to error checking in processor systems.
Error correcting code (ECC) and parity checking are techniques used to detect and, in the case of ECC, correct a subset of possible errors in information systems. These techniques are especially useful in computer systems. As the voltages and the dimensions of semiconductor logic are reduced and the areas consumed by semiconductor chips are increased, the opportunities for errors in a computer system increase. Common causes of errors in semiconductors are noise (e.g., power supply noise and EMF-induced noise), logic failure, and the effects of energetic particles, which can flip bits and destroy logic. Electromagnetic fields (EMF) can be generated by high semiconductor clock rates, fast changes in current magnitude and direction, and external fields generated in the local environment (e.g., lightning strikes and microwave radiation). Low voltages used to power semiconductors decrease energy consumption and facilitate small semiconductor dimensions but decrease the voltage difference between a logic 1 and a logic 0, increasing a circuit's susceptibility to noise. Soft failures are transitory while hard failures are permanent.
Parity is a widespread technique used to check data for an error whereby a bit is appended to the end of a bit-pattern to indicate whether there is an odd or even number of logic 1's in the bit-pattern. For example, the bit-pattern 10101010 can have a logic 0 appended to it, called the parity bit, to indicate that it has an even number of 1's. If one of the bits in the bit-pattern is flipped, the parity bit will be incorrect, and indicate an error. However, if two bits are flipped, the errors will go undetected as the parity bit will be correct. ECC uses a more complicated encoding with which multiple bit errors can be detected but it requires that multiple bits, called check bits or check-data, be associated with the bit pattern.
While error checking can significantly increase the reliability of computations, a disadvantage of ECC and parity checking is that their functions consume logic and therefore chip area that is often located in a region of a processor whose fast operation is critical to high performance. The area consumed by parity and ECC checking logic tends to physically spread out and separate critical logic that would otherwise be in close proximity (e.g., register file and functional unit logic), increasing signal propagation delay across the logic. This decreases performance and/or requires an increase in energy consumption to maintain a short signal transfer time over a larger chip area.